资源列表
Buf_FiFo
- verilog 编写的FIFO，里边有IP核和控制模块，-verilog write FIFO, inside the IP core and control module,
Lab-1
- Design and simulate D flip flop with reset button. Objectives Explore Modelsim through a simple circuit design.
Lab2
- Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim
Lab3
- Sequential binary Message detector Objectives 1. Working with finite state machines. 2. Defining user types in VHDL
Lab4
- RAM design Objectives 1. Working with generic units. 2. Working with Arrays 3. Working with integers
fir25
- 用VDHL写的25阶对称FIR滤波器，在塞克隆3FPGA下验证没有问题（AD采样时钟50Mhz，这个对硬件设计有点要求），里面调用官方乘法器API，要节省资源可以采用CSD编码转换乘法器，可以减少一半以上的资源-VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit
fir_csd
- vdhl实现FIR，乘法器采用CSD编码，在资源紧张情况下，可省去很多资源-vdhl achieve FIR, multiplier using CSD coding, in the case of resource constraints, can save a lot of resources
uart_test
- altra fpga nios 开发uart工程-UART IP and test on nios
traffic-light-FPGA
- FPGA做的路*通灯的完整实验，得到了全班最高95分，讲解详细，附工程文件，手把手教您-FPGA do traffic lights at the junction of the complete experiment, the class was up to 95 points, explain in detail, with engineering documents
fuzzy_rulebase
- fuzzy rulebase
defuzzification
- fuzzification
SingleCycle8bitProcessor
- Simple 8-bit Single Cycle Processor in Verilog HDL