资源列表
ALU_VERILOG_COCOTB
- ALU written in Verilog HDL and tester written in python using the cocotb library
SystemVerilog_3.1a
- system Verilog language reference manual
SV-Tasks-a-Functions-Intro
- system Verilog tasks & functions introduction
SV-Priority
- system Verilog priority
SV-Combinational-Logic
- system Verilog combinational logic
VGA
- Verilog实现VGA 6408480@60(Hz)-Verilog implements VGA 6408480@60(Hz)
SEG_CLOCK
- seg clk seg clk seg clk-seg clkseg clkseg clkseg clkseg clk
CST_-_hokej
- VHDL school work. Display ice-hockey scores and time on 7seg display.
CST_-_Smajlici
- VHDL school work. Display four smiles on 8x8 matrix display. It use four button to :--VHDL school work. Display four smiles on 8x8 matrix display. It use four button to :-))
alphabeta_transform
- alpha beta transformation, for FPGA synthesis and implementation
myAdc9248
- CycloneIV控制采样芯片AD9248-20MHz，VHDL语言-CycloneIV control sampling chip AD9248-20MHz, VHDL language
ROM
- FPGArom的IP核使用及仿真,Verilog语言，非常详细-IP core and use of simulation FPGArom, Verilog language, very detailed