资源列表
crc7_4
- 使用Verilog HDL语言按标准编写的CRC（7,4）循环码，对学习编码有很好的指导作用！-Verilog HDL CRC(7,4) coding
Altera-Recommended-HDL-Coding-Style
- Altera 推荐的HDL编码风格，在学习HDL的时候比较重要，另外对HDL到RTL的映射有一定的帮助。-Altera Recommended HDL Coding Style
nand_interface_con
- NAND FLASH 控制器 功能强大 性能稳定 接口简单 适合使用-NAND FLASH control
RISC-CPU
- 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放
xilinx_ise_14
- this the xilinx_ise_14 s license!after you have setuped the software,the license will very helpfull! the xilinx_ise_14.lic file ,xilinx_ise_14 license-this is the xilinx_ise_14 s license!after you have setuped the software,the license will very he
Double_FPU
- 详细介绍双精度浮点数据的格式，以及加减乘除运算的实现方法-Details of the format of double-precision floating-point data, and the realization method of addition and subtraction multiplication and division
ARM_register
- ARM寄存器组设计的源代码，使用Verilog编程实现，可以编译仿真通过。-将中文译成英语 ARM register set design source code, the use of Verilog programming, you can compile the simulation pass.
pn127
- 这是个128位的串行伪随机码发生器，还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
URAT
- Verilog硬件描述语言，RS232串口发送接收程序-Verilog hardware descr iption language, RS232 serial port send and receive program
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
Verilog
- verilog digital clock
Booth_4
- 用VERILOG 编写的弹球游戏，其中涉及到VGA协议和接口开发设计-Written with the VERILOG pinball game, which involves the development and design VGA protocols and interfaces