资源列表
Verilog
- fpga使用代码大全，很有用的，，谢谢下载，我没什么说的了，住学习愉快-fpga using the Code Complete, very useful, Thank you to download, I have nothing to say about it, learning to live happily
TFT
- 3.5寸TFT FPGA驱动程序,2C8驱动扫描TFT屏实现色条-TFT DV for FPGA
clock
- 数显时钟编码，verilog 代码实现，其中含有测试文件-Digital clock code, verilog code, which contains the test file
NCO
- 用verilog语言写的NCO，在quartus环境中应用-Verilog language written with NCO, quartus environment in the applications
4_31
- 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
AD637
- 芯片AD637的应用！自己在实际中使用过!就是根据这个资料！-AD637 chip applications! Their use in practice over! Is based on this information!
verilog
- 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
ps2_keyboard
- FPGA PS2键盘驱动设计，使用软件QuartusII6.0 verilog-FPGA PS2 keyboard-driven design, the use of software QuartusII6.0 verilog
liftvhdl
- 四层电梯vhdl 1、 每层电梯的入口处设有上下请求开关，电梯内设有乘客到达层次的停站请求开关。 2、 设有电梯所处位置指示装置及电梯运行模式（上升或下降）指示装置。 3、 电梯每秒升降一层。 4、 电梯到达有停站请求的楼层后，经过1s电梯打开，开门只是灯亮，开门4s后，电梯门关闭（关门指示灯灭），电梯继续运行，直至执行完请求信号后停在当前楼层。 5、 能记忆电梯内外的所以请求信号，并按照电梯运行规则依次响应，每个请求信号保留至
cpu
- verilog编写的简单的CPU，用于参考，已经过仿真-verilog prepared by a simple CPU, for reference, has been simulation
VHDL
- 8位相等比较器含源代码，用VHDL语言编写，具体很高的实用性，供读者参考-8, phase comparator, such as with the source code, using VHDL language, the specific relevance of a high for the reader is referred to
color_conv
- BT656,YCBCR数据格式转换成VGA(888)数据算法，-BT656, YCBCR data format converted into VGA (888) data algorithm,