资源列表
state-machine
- 一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理-A simple realization of a vending machine with verilog state machine design, there are design principles introduced word
Synchronous-FIFO-
- 一个用verilog实现的同步fifo设计，压缩包里有word介绍设计中各信号的作用-Achieve a synchronous fifo with verilog design, compression bag has the role of word describes the design of the signals
MIPS
- 用verilog编写的简单的类MIPS多周期流水化处理器实现，基本功能包括9条指令和两位动态分支预测，压缩包里的word详细说明了结构中的细节-Written by verilog simple class multi-cycle pipelined MIPS processor, the basic features include 9 instruction and two dynamic branch prediction, compressed bag word specifies th
stopwatch-design-and-verification
- 一个具有秒表功能的模块，具有计时、清零、暂停等功能，精度为0.01s-The module has a stopwatch function, with time, cleared, pause function, accuracy 0.01s
VHDL
- 彩灯控制器设计 彩灯控制器设计 彩灯控制器设计 -Lantern controller design lantern controller design lantern controller design lantern controller design lantern controller design lantern controller design
sales
- 自动售货机，与现实生活中的售货机功能类似，可以自动进行找零-Vending machines, vending machines and similar real life, there is a function to automatically calculate the price of goods
RECEIVER
- 此程序为基于OFDM的802.11a的接收端的VERILOG代码，包含所有模块。-This program is VERILOG code receiving end 802.11a OFDM-based, including all modules.
TRANSMITTER
- 此程序为基于OFDM的802.11a的发送端的VERILOG程序，包含所有模块。-This program is VERILOG program sender 802.11a OFDM-based, including all modules.
Perfect-Timing-II-Book
- 该文档为英文的完美时序一书，写的很好，对FPGA时序设计很有帮助。-This document is the perfect timing of the English book, well written, useful for FPGA design timing.
A-(2)
- A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL-A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL
hdb3
- hdb3编解码程序，非常简洁好用，欢迎下载-hdb3 codec program is very simple to use, welcome to download
Desktop
- 此程序为矩阵键盘驱动Verilog程序，带键盘模型和仿真平台。-This is a matrix keyboard driver, Verilog, with simulation models and simulation platform