资源列表
SERIALADDER
- SERIAL ADDER 8-BIT-SERIAL ADDER 8-BIT
SCCB_Control
- 两线式SCCB总线FPGA驱动，verilog语言编写，可用于配置OV系列摄像头-Two-wire bus SCCB FPGA drive, verilog language, can be used to configure the OV series camera
mux_structural
- 8 to 1 16bit mux code for ECE585 of IIT
epm3128a
- dsp28335，索思达电子开发板28335evm-1开发板搭载的CPLDepm3128a的VHDL核心源代码-dsp28335, Suo Sida electronic board 28335evm-1 development board equipped CPLDepm3128a of VHDL core source code
freq_div
- //奇数倍分频器基于verilog HDL.-(ODD number)Freq Divider based on Verilog HDL.
SDRAM_Verilog
- 本源码由Verilog语言编写，用硬件实现SDRAM的读写和存储数据功能，包括SDRAM的控制模块、初始化模块、读写模块等！-The source the Verilog language, implemented in hardware SDRAM read and write and store data, including SDRAM control module, initialization module, reader module, etc!
AD0804LC
- 使用VHDL语言完成了ADC0804程序,设定阈值，过阈值报警。附带了整个工程文件-with VHDL language,it can work with ADC0804
LCD12864jibenxianshichenggong
- fpga驱动lcd12864文字显示基本成功-fpga Niuguidongpu ﹍cd12864 Wenxiaoquandie ч Shao Bao Ji с Tuokun ╃ Ebanpanyi
3weishuru8weishuchuyimaqi
- fpga基本操作程序3位输入8位输出译码器-Bao Kun ╃ fpga Ebanmuyou Tongtizipin
Altera_Audio
- 针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。-The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.
led
- 控制4盏灯从左到右依次点亮循环，这是基于系统驱动的开发，可用于嵌入式系统的学习-Control 4 lamps were lit left to right cycle
uart
- 这是用键盘控制led灯的点亮和熄灭，还可以控制蜂鸣器的响，可用于嵌入式的学习和开发-This is controlled by the keyboard led lights on and off, you can also control the buzzer sound can be used for embedded learning and development