资源列表
8051
- 介绍了新的声音采集方法，利用VHDL编写，对声音频谱分析有很强的拟合性-Introduced a new sound collection methods, the use of VHDL writing to sound spectrum analysis has a strong fit of
CPU_single-(2)
- 单周期CPU设计源码，基于Quatus II，亲测可用-Single-cycle CPU design source code, based on Quatus II, pro-test available
ataninfpga.rar
- 基于FPGA的快速反正切运算实现方法可以用于解调的相位计算,Fast FPGA-based computing arctangent demodulation method can be used to calculate the phase
S12_AudioLoopback_DAV_MIC
- 从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code
tes_amp_80_0314
- 基于dsp builder的数字下变频器，IP核做的-digital down converter,degigned in matlab
traffic_3
- vhdl语言编写的红绿灯控制系统，分红黄绿灯和直行，左右转的状态，已调通-language vhdl traffic light control system, dividends yellow green and straight, turn around the state, has been transferred Qualcomm
fifo
- 异步FIFO是一种先进先出的电路，使用在需要产时数据接口的部分，用来存储、缓冲在两个异步时钟之间的数据传输。- Asynchronous FIFO is the electric circuit which one kind advanced leaves first, uses when needs to produce data interface s part, uses for to save, the cushion between two asynchronous clock s d
FPGA-debugging-techniques
- FPGA常用调试技术，对ISE中各种错误的详解。-FPGA debugging techniques used on a variety of errors in the Detailed ISE.
debugging-of-FPGA
- 以ISE为例，介绍FPGA的高级调试技术，中文，适合具有一定基础的-The ISE as an example, advanced debugging of FPGA technology, Chinese, has a certain foundation for
edk_for_busy_people
- XILINX 出品 EDK快速学习资料。 EDK在 Xilinx FPGA上构架一个CPU软核， 以提高整个系统的灵活性，和可扩展性。-EDK document by Xilinx. EDK is used to build a soft CPU Core on XILINX FPGA.
gray
- 基于Verilog的GRAY计数器。以及测试文件，在simulation的文件件中的top文件。-Based on Verilog, GRAY counter. And test files, the files in the simulation of the top pieces of the file.
auk_rtprx-v3.1.0.tar
- The Altera(R) RTP Receiver function implements a buffer for received RTP packets. Duplicated and re-ordered packets are corrected. Missing packets can be fixed using Pro-MPEG Code of Practice #3 Forward Error Correction