资源列表
Altera_Quartus_6.0_crack
- fonctional crack of VHDL describer Quartus 6.0
29_ad9226_test
- ad9226相关FPGA程序VHDL源代码，可直接用！-Ad9226 related FPGA program VHDL source code, can use directly!
stopwatch
- 具有计时功能。此秒表有3个按键（reset， start,select）按下reset键后，秒表清零，按下start键后，开始计时， 再次按下start键后， 停止计时，按下 ，可以轮流切换显示秒和分钟，百分一秒。-With timing function.This stopwatch has three buttons (reset, start, select) after pressing the reset button, a stopwatch reset, press the sta
lvboqi
- 数字滤波器的FPGA的实现和源代码以及仿真-FPGA implementation of digital filters and source code
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
IAR
- 数字频率计 msp430 f6638 和 fpga 的开发板 使用fpga来计算频率 使用430 来显示控制-The digital frequency meter f6638 MSP430 and FPGA development board use FPGA to calculate the frequency using 430 to display control
snake
- 贪吃蛇小游戏，利用FPGA，在显示屏上显示贪吃蛇游戏，由键盘来控制-Snake game
fpga_FILTER
- 基于FPGA的可编程数字滤波器系统,基于FPGA的数字滤波器的设计与实现,基于FPGA流水线分布式算法的FIR滤波器的实现-FPGA-based programmable digital filter system, the digital filter based on FPGA Design and Implementation, Distributed Pipelined FPGA-based FIR filter algorithm to achieve
designreport
- 简易自动售货机，带led动画，可进货找零选择不同商品-Easy vending machines, with led animation, the change may choose to purchase different commodities
05_ledtimer
- 数码管显示的时钟,verilog HDL 基础教程-a timer basied on led
vga_automove_img
- VGA输出的图像，可以使图片在屏幕上自动碰撞移动。硬件语言-The VGA output image, the picture on the screen automatic collision mobile. Hardware language
jtd
- 基于VHDL语言的交通灯设计，主控平台为Xilinx-basys2，适合初学者研究-Traffic lights based on VHDL design, master platform for Xilinx-basys2, suitable for beginners research