资源列表
tony_wu
- Verilog HDL程序 Verilog HDL程序-Verilog HDL procedural procedures Verilog HDL
rs1_7seg_pci-0.0.1.tar
- Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd. -Raggedstone1 IP core.Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
write_io
- DSP EMIF 扩展io程序 DSP EMIF 扩展io程序-DSP EMIF procedures to expand io expansion io procedures DSP EMIF
select_32
- 32位 2选1 选择器 VHDL语言程序-32 2 election 1 selector VHDL Language Program
write_rd
- 关于VHDL的 关于DSP的 emif-On VHDL on the DSP s EMIF
vhdl00023kejian
- VHDL课件 张建老师的精彩课件讲述了，中国著名的嵌入式开发人 -VHDL courseware courseware wonderful teacher Zhang Jian told China s well-known embedded development people
wervhdl
- 赋值语句有两种，即信号赋值语句和变量赋值语句。每一种赋值语句都有三个基本组成部分，即赋值目标、赋值符号和赋值源。信号赋值语句和变量赋值语句的语法格式如下 :-There are two assignment statements, that is, the signal assignment statements and variable assignments. Each assignment has three basic components of the assignment objec
freq
- vhdl语言设计频率计，十进制加法器.运用maxplus2运行，-VHDL language design frequency, the decimal adder. maxplus2 application running,
millerdecode(050710)
- 有源代码，modelsim仿真通过，并有介绍文档。-Active code, modelsim simulation through, and to introduce the document.
beep
- 一个verilog程序，写的完善，有注释，与其他蜂鸣器程序有较大改进，希望对初学者有帮助-A Verilog program, written by well-annotated, buzzers and other procedures have greater improvements in the hope to be helpful for beginners
VHDLanli
- vhdl源码案例， vhdl源码案例，-VHDL source case, vhdl source case,
CPLDforCCD
- 基于CPLD的光积分时间可调线阵CCD驱动电路设计-CPLD-based optical integration time adjustable linear array CCD Drive Circuit Design