资源列表
lock
- 电子密码锁，实现并行输入，错误报警和密码设置功能，以及兼作门铃使用-Electronic code locks, the realization of parallel importation, error alarm function and password settings, as well as the use of doubles as a doorbell
VerilogHDL
- 这是一本pdf格式的电子书，书名是VerilogHDL，将一种硬件描述语言-This is a pdf format e-books, the title is VerilogHDL, will be a hardware descr iption language
modelsim
- modelsim 使用教程,verilog或vhdl仿真-ModelSim use tutorial, verilog or VHDL simulation
shifter
- 完成一个加速器设计，全加器，具 8位计数器-Complete a accelerator design, full adder, an 8-bit counter
timer
- VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
121111
- 关于FPGA和单片机的PCB板的开发原理图，以及相关的单片机程序设计-On the FPGA and PCB MCU development board schematics, as well as related Singlechip Programming
doc
- VHDL：用状态机的方法实现一个8位乘法器-VHDL: state machine method used to achieve an 8-bit multiplier
SOC_CCD
- 基于SOC 的线阵CCD 图像采集单元设计，关于ccd的资源-SOC based on the linear array CCD image acquisition unit design resources on the ccd
VHDL
- vhdl学习总结的文章，初学者建议多看看哦。-VHDL study summed up the article, recommends beginners take a look at multi-Oh.
cnt_fry
- 本程序功能是由VHDL语言实现对频率的测量，然后用数码管进行显示-The program features by the VHDL language to achieve the frequency of measurement, and then use the digital tube display
div_2n
- 此程序实现的是任意进制的分频 进制的输入是任意选择的-The realization of this procedure is arbitrary frequency-band sub-band input is optional
ethernet_example
- FPGA上实现以太网 用VHDL实现，欢迎多交流 -FPGA to achieve the realization of Ethernet using VHDL welcome more exchanges