资源列表
Keyboardcontroller
- keyboardcontroller IP CORE .VERY GOOD AS A STUDY FILE-keyboardcontroller IP CORE. VERY GOOD AS A STUDY FILE
FFTProcessor
- IP CORE .VERY GOOD AS A STUDY FILE-IP CORE. VERY GOOD AS A STUDY FILE
firewire
- IP CORE .VERY GOOD AS A STUDY FILE-IP CORE. VERY GOOD AS A STUDY FILE
VHDLtlight
- 智能控制交通灯。分主路辅路，当辅路无车时主路保持绿灯，当辅路有车通过时辅路亮绿灯，并且在最短五秒钟之后或者20秒之内返回原来的状态。-Intelligent control of traffic lights. At the main road and side roads, as roads without the green light when the main road to maintain, when the roads when the roads a car through a
ask
- 提供一个把通信中ASK调制用VHDL来实现的例子，内附有相应的VHDL源程序。-To provide a communication ASK modulation achieved using VHDL example, enclosing a corresponding VHDL source code.
DCT2IDCT2
- CT2 IDCT2 变换C代码。经调试成功，适用于altera,有结果。-CT2 IDCT2 transform C code. After successful testing for altera, bear fruit.
cordiccos
- 改进的cordic算法的迭代cos结构，适用于altera。-Improved Iterative CORDIC algorithm cos structure, applicable to altera.
multiply
- 由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。-Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
cpu
- cpu的vhdl设计实现加法减法乘法运算-cpu VHDL Design and Implementation of multiplication addition subtraction
poc1
- poc的VHDL详细设计 实现握手信号的交互 -poc of VHDL handshake signal to achieve the detailed design of interactive
polar2rect_VHDL
- 是codic算法实现atan的virilog程序，模块结构如下：Core Structure: sc_corproc.vhd->p2r_cordic.vhd->p2r_cordicpipe.vhd-Atan is the codic algorithm virilog procedures, module is structured as follows: Core Structure: sc_corproc.vhd-> p2r_cordic.vhd-> p2r_cord