资源列表
FPGAshilier
- 各种fpga的开发资料，非常适用，实在是难得的资料，对于初学者非常有帮助-The development of a variety of FPGA information, very useful, it is hard to come by the information very helpful for beginners
USB_FT245
- 在altera fpga cycloneIII EP3C5E 上实现了对USB 245的通信。-In altera fpga cycloneIII EP3C5E on the realization of the USB 245 communications.
DS18B20
- 基于VerilogHDL开发的DS18B20温度传感器实验程序。-VerilogHDL developed based on experimental procedures DS18B20 temperature sensor.
VHDL
- 数字电路实验程序代码打包下载 版本 宁波大学学年数字电路实验 VHDl编程 部分 -Digital circuit experiment program code package download version Ningbo University academic year programming section VHDl digital circuit experiment
FPGA
- 是一位FPGA大牛写的FPGA杂谈，详细介绍了玩转FPGA的流程和他对FPGA的理解，语言风趣幽默，见解独到深刻。-Is written by a FPGA and FPGA gossip, embracing the FPGA was introduced in detail the process and his understanding of the FPGA, humorous language, independent-minded.
Day3
- 关于FPGA的文档，通过此文档可以更好的学习FPGA的运作和开发。-Documentation on the FPGA, through this document can better learn the operation and development of FPGA.
pwm
- 运用FPGA 产生pwm脉宽调制信号的源代码-use fpga generate pwm signal
5.1-PCF8563
- 基于pcf8563的数字钟设计，erilog语言编写，以调试-digital clock based on erilog langrage
ASI_IN1_and_ASI_OUT1
- 这是对于从卫星接收下来的TS流，有两路流，对其选择，其中包括同步模块，PCR校正模块，码率调整模块-This is received from the satellite down for the TS stream, there are two streams of their choice, including the synchronization module, PCR correction module, rate adjustment module
Cadence-Encounter
- 8x8 mulitplier. created this file using the midelsim softwre. Tested and simulated. Great waveform, so the testbench is included also. Does anybody knkow how to make a 16x16 arrray multiplier?
sdram
- SDRAM 的读写，在仿真版上测试过的 可以用，源码+控制逻辑-SDRAM read and write, tested in the simulation version Can use the source code+ control logic
TX
- In data transmission and telecommunication, bit stuffing (also known—uncommonly—as positive justification) is the insertion of noninformation bits into data. Stuffed bits should not be confused with overhead bits. Bit stuffing is used for variou