资源列表
phase
- 本文表述了怎样进行信号的移相等问题的研究，设计到代码的书写-this paper describe how to move phase
verilog-code
- 都是verilog代码：多路选择器代码，储存器代码，时钟分频器代码，串并转换电路代码，香农扩展运算代码，ram代码。-MUX code and REGISTER code clock divider code string conversion circuit code, Shannon extended op code, the ram code.
DDS
- 毕业设计，基于FPGA的DDS设计与实现模块-FPGA DDS
FPGA_SDRAM
- 这个工程主要使用FPGA来对SRAM简单快速的操作，使用的是IS62LV256-70U芯片，文件中含有该芯片的datasheet-The project is mainly used for SRAM FPGA to a quick and easy operation, use the chips IS62LV256-70U, the file containing the chip' s datasheet
FPGA_JOW
- 本设计为学校打铃管理系统，使用VHDL设计，根据打铃功能不同输出不同的音乐,工作模式包括正常上课模式、考试模式、放假模式-The design management system for the school bell, the use of VHDL to design, according to different output different music in Bell functions, working modes including normal class mode, test
15_IP_core
- ata, 3des vgs等ip核。 ECE395 GPU: -ata, 3des vgs and other ip core. ECE395 GPU:
256MbDDR2
- 对ise的应用进行了具体的描述，而且把一些我们未涉及的功能进行了介绍，是一本好书。-Ise the application of a specific descr iption, and we have not covered some features were introduced, is a good book.
32bit_RISC_CPU
- 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
vga2
- 一个简单的小球挡板游戏，通过VGA接口可在显示屏上显示，支持双人对战-A simple ball game baffle, through VGA interface can be displayed on the display screen, supports double play
sdk_memory_test
- 内存测试程序，包含完整的源码。在xilinx的sdk环境下运行-Memory testing procedures, including complete source code. Run under the xilinx sdk environment
dianziqn
- 电子琴的代码，可以自己即兴演奏的电子琴，基于vhdl语言实现，音色很不错啊-e-piano based on quartusII and designed by vhdl language
vga_display
- verilog实现vga显示，板子上验证正确性-verilog achieve vga display, verify the correctness of the board