资源列表
LCD1602
- 写的一个用lcd1602的随机数发生器，用的语言为Verilog，工具是Quartus II软件。-Write a random number generator with lcd1602, the language used for the Verilog, Quartus II software tool.
FILTRO_DIGITAL_EN_VHDL
- DIGITAL FILTER IN VHDL FOR XILINX FPGA SPARTAN 3
sdram_mdl
- FPGA控制SDRAM程序，包括初始化、读写-SDRAM Initial and Read Write
Desktop
- 频率检测，verilog hdl,单片机用C8051F120外部中断0。测量范围2Hz到9MHz-Frequency detection, verilog hdl, C8051F120 microcontroller with external interrupt 0. Measuring range 2Hz to 9MHz
VHDL
- 通过学习此文件，了解VHDL的基本语法，并且能够编写一些简单的程序-By learning this file ，you can know some basic grammer of VHDL and coding some simple program
quartus_project
- verilog的一些代码，都是自己写的，欢迎拍砖-verilog some of the code is written in his welcome Paizhuan
LwIP_raw_apps_sdk
- Vivado sdk raw mode app to implement LwIP
shiyansan
- 简易数字频率计 实验设计 数字系统设计 采用模块化设计 -Simple digital frequency meter experimental design digital system design is modular in design
altfp_mult_DesignExample_ex
- 浮点数乘法 verilog语言编写 可直接调用-Floating-point multiplication verilog language
uartsample
- Xilinx EDK开发 通过FPGA实现UART通信-EDK Xilinx development through FPGA to achieve UART communication
alucpu
- 计算机组成实验 西南交大 alu运算器 计算机组成实验 西南交大 alu运算器-Computer Composition experiment Southwest Jiaotong University the alu computing device
my_RAM
- pdf actel fpga verilog ram读写-pdf actel fpga verilog ram read and write