资源列表
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
stepmot
- verilog for control motor
crc_8
- 用vhdl编写的CRC校验代码，仿真以及下载在板上测试通过-Prepared by the CRC checksum vhdl code, simulation, and download the on-board test
counter
- 六十进制计数器，自动进位，有点小错，实在改不过来了-Six-decade counter, automatic bit, a little wrong, but it changed to a
HDMI_test
- 基于Xilinx的FPGA的spartan3的HDMI测试功能刷屏显示。-Based on Xilinx s FPGA spartan 3e of the HDMI display refresh function tests.
dianti
- 该程序实现的功能是：基于VHDL语言的电梯控制器
AD8522_SPI
- AD8522模拟数字转换芯片sdi接口配置代码-AD8522 analog-digital converter chip sdi interface configuration code
alert
- eda电子钟闹钟模块的实现 -digital clock alert digital clock alert digital clock alert digital clock alert
firfilter
- FIR滤波器：自定滤波器的类型（低通，高通或带通）、设计指标（通带截止频率、通带波纹、阻带截止频率、阻带衰减） 1、根据指标选择合适的窗函数，用窗口设计法设计符合指标的FIR滤波器；并验证其性能是否满足预定指标。 -FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, st
7Segment
- vhdl seven segment code
count_free
- 本程序是实现在用电话卡打电话时进行自动计费的功能，包括检测通话的种类，时间和余额检测等多项功能，此代码用veriloghdl编写已经调试通过编译。-Implementation of this procedure is used when the phone card to call the function of automatic billing, including the detection of the types of calls, time and number of functi
VHDL_PWM
- FPGA的PWM產生程式碼，以及一個判斷是否直接輸出，或是使用指剝開關限制輸出。-Produced both PWM, and a direct output to determine whether or limit the use of means stripping switch output.