资源列表
eda-chengxu
- VHDL语言源程序，使用元件例化的方法设计简易数字钟-VHDL language source code, the use of components instantiated designed simple digital clock
Exp8-GAME
- FPGA小游戏，代码内部说明清晰，可自习斟酌-FPGA game, code clarity of internal notes, as appropriate, to study
led
- 一个简单的在fpga上实现循环跑马灯的程序-A simple cycle in the FPGA to achieve the procedure Marquee
CycloneDeviceHandbookVolume
- 这是一个关于FPGA cyclone 的数据手册。-This is a FPGA cyclone on the data sheet.
cos
- FPGA实现正弦，余弦的计算，verilog语言-FPGA realization of sine, cosine calculation, verilog language
LABVIEW制作的电子时钟软件
- 电子时钟软件，使用LABVIEW制作的电子时钟软件具有优美的界面-Electronic clock software, produced using the LABVIEW software electronic clock with a beautiful interface
24_bit_register
- 自己使用VHDL语言编写的24位寄存器.主要用于DDS中-24bit_register
PCK_CRC32_D8
- VHDL实现的8位数据，CRC32的实现代码，简单实用-VHDL achieve 8-bit data, CRC32 implementation of the code, simple and practical
FPGA_experience
- FPGA设计经验总结，对你的FPGA设计能力将有很大的提高-The summary of FPGA s design, it will be a great improve to your ability of designing FPGA
i2c
- 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl
verilog_18bit_Div
- verilog编写的18位输入高精度的除法器，带说明文件和测试代码。-18 input precision divider verilog prepared with documentation and test code.
iic
- 单片机和cpld通信中的用vhdl编写的cpld源程序代码-Cpld single-chip computer and communications cpld prepared using vhdl source code