资源列表
Verilog数字系统设计教程
- Verilog教程 数字系统设计 夏宇闻(Verilog Digital System Design)
ex5
- FPGA测试频率，传统测频率,verilog语言，短程序，测频法测频率(using FPGA verilog language a short code for frequtents)
SDRAM
- 使用VHDL语言编写的对SDRAM进行读写操作控制器及其简单的测试层序。(VHDL language used to read and write operations controller SDRAM and its simple test sequence.)
clock_sel
- 无毛刺多时钟选择，可根据不同模式选择不同时钟(Multi clock selection, different modes can be selected according to different clock)
rs_code
- FPGA实现了RS（255，239）的编译码模块(FPGA implements the RS (255239) encoding and decoding module)
Quartus_12.0_x64
- quartus 12 "solution"
Quartus_12.0_x86
- quartus 12 "solution" 2
QuartusII91_
- quartus 9 "solution"
QII_9.1.tar
- quartus 9 "solution" 2
HEX2BCD
- 十六进制转BCD,包含设计文件和仿真文件，工程文件(Sixteen decimal to BCD, including design documents and simulation files, engineering documents)
sine
- 基于FPGA产生正弦波信号，频率可控，很有用(FPGA based sine wave signal generation, frequency control, very useful)
Dividers
- 文件中包括各种除法器，不同类型的，不同算法的。(The document includes a variety of divider, different types, different algorithms.)