资源列表
ad7606_evalboard
- 在nios2中实现对AD7606的采样控制(Sampling control of AD7606 in nios2)
uart_2_led_ego1
- 通过uart接受到一个8位的数据，在fpga ego上面用led显示出来(Receive a 8 bit data through UART and display it on FPGA ego with LED)
hamming
- verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)
axi_lite_user
- axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)
RGBtoYUV
- BMP格式文件的RGB数据转换为YUV格式。(Transform RGB data of a bmp to YUV.)
VHDL实用教程_潘松_王国栋
- VHDL语言入门学习资料，非常赞，看了觉得很值!(This is a good tutorial for learning VHDL language. Very suitable for beginners to learn)
串口通信
- 该程序主要实现FPGA串口通信，包含源码和串口调试工具(The program mainly to achieve FPGA serial communication, including source code and serial debugging tools)
SPI_master
- spi-master模块的verilog(simple program for SPI-Master)
FPGA TFT 驱动
- 用于 驱动TFT的FPGA代码。该代码是用VHDL编写。(FPGA code for driving TFT.)
spi
- spi原理的详细说明及verilog实现(SPI principle and its implemetation in verilog HDL)
AD9512_coe
- AD9512 提供多路输出时钟分配功能，输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性，能够极大地提升数据转换器的时钟性能。(AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the cl
AD9512_ISE
- AD9512提供多路输出时钟分配功能，输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性，能够极大地提升数据转换器的时钟性能。(AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clo