资源列表
Clock generator
- A clock Generator in verilog
Chapter 4
- codes and simulation of chapter 4
Chapter 8
- verilog code and simulationsof chapter4
src
- Digit serial adder, can be used in digital filter design You can choose the pipeline length, digit size and the word length of the adder.
PmodHMT
- Demo 使用 PmodHMT 模块实时检测环境温度和湿度。(The Demo uses PmodHMT modules to detect environmental temperature and humidity in real time.)
xa880
- Join repetitive control, Very convenient to use, Iterative self-organizing data analysis.
m_sequence
- 基于fpga verilog语言生成的m序列。(Generating m sequences based on FPGA)
full_license
- quartus9.0 全功能license(quartus9.0 full license)
VHDL——如何写简单的testbench
- 基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)
Helloworld
- VERILOG HDL HELLO WORLD
c_crc16
- CRC 16 development code
spi_vip
- SPI verifcation in sv