资源列表
Digital_Clock
- 用verilog写的数字时钟代码，亲测可用，可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
sp6ex19
- FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA examples of FIFO, FPGA on-chip FIFO reading and writing test)
apb.v
- AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
hidejj
- 实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
CPLD
- 数字频率计在FPGAEP4CE10F17C8上的功能实现和运用(Application of digital cymometer in FPGA)
CPLD
- CPLD的介绍，请认真看，很基础，可以打印出来(CPLD introduction, please look carefully, very basic, you can print out)
FIFO Design Using Verlilog
- DFF with fifo concepts
FIFO Details
- FIFO Design PDF files
m-test
- 产生小m序列，用于扩频系统中，仿真测试正确，反馈级数为4(Generating m sequences)
Altera FPGA_CPLD设计_高级篇【www.ourfpga.com】
- Altera FPGA_CPLD设计_高级篇,对fpga的提高很有帮助(can improve the application of fpga)
BMD_design_gen2_x4_with_Chipscope
- PCIE BDM官方实例，xapp1052(PCIE BDM XAPP1052 FROM XILINX)
TankWar
- 使用Verilog语言在ise平台上实现的坦克大战游戏，实现了基本的游戏功能(The use of Verilog language in the ISE platform to achieve the tank war game, to achieve the basic functions of the game)