资源列表
altera_fft
- alter官方fft程序 使用verilog编写 需要的同学可以下载-alter the official fft program uses verilog prepared students in need can be downloaded
uartfifo
- 基于FPGA的串口发送源代码，通过FIFO能够发送一段字符串。-FPGA-based serial port source code, a string can be sent through the FIFO.
Mentorkg_2010
- Modelsim 6.6 破解，Windows & Linux通用-Modelsim 6.6 crack, can be used for Windows/Linux edition.
uart
- 利用串口调试助手是实现pc机和fpga的串口通信功能，程序附注释。-Debug Assistant is achieved using serial pc machine and fpga serial communication function, the program annotated.
iir
- 基于verilog HDL的IIR数字滤波器的实现-Verilog HDL-based implementation of the IIR digital filter
counter32
- 基于VHDL的方波产生代码，根据占空比的不同，输出不同方波-Based on square wave generated VHDL code, according to the different duty cycle, the output of different square-wave
FPGA_UART
- 其中讲到的是经典的VHDL的UART设计实例，而且有很详细的解释和分析，适合针对FPGA串口的开发。-Which is referred to the UART VHDL design of the classic examples, and there are detailed explanation and analysis for the serial port for FPGA development.
gen_displayer
- 基于线性反馈移位寄存器电路，并结合FPGA 的特有结构，一种简捷而又高效的伪随机序列产生方法-The Implementation and Research on Pseudo-Random Number Generators with FPGA
example19
- 基于FPGA的数码锁 基于FPGA的数码锁 -FPGA-based FPGA-based digital lock digital lock digital lock-based FPGA
AlteraUSBBlaster
- Altera USB Blaster的电路图.很详细，适合DIY-Altera USB Blaster schematic. In great detail, suitable for DIY
dsp-builder-7.2-crack
- 5款altera的FPGA开发板原理图，详细介绍了板子的构成及功能-Altera paragraph 5 of the FPGA development board schematics, detailed information on the composition and functions of board
Qsys_nios2
- 本教程使用最新的Quartus 11.0sp1+Nios 11.0sp1开发工具。在最新的Quartus II软件中，使用了全新的Qsys进行SOPC系统的构建。 较之以前版本使用SOPC Builder构建有了很大的不同。 本教程为Altera最新的官方Tutorial。 一步步教你使用Qsys构建Nios II系统，并使用Nios II SBT开发应用程序。-This tutorial uses the latest Quartus 11.0sp1+ Nios 11.0sp1 d