资源列表
DE2_pong_demo
- de2,altera fpga开发板，自带的源码，pong_demo-de2, altera fpga development board, comes with source code, pong_demo
calculator
- 用VHDL在quartus2下实现的计算器。输入为4*4矩阵键盘，输出为共用数据线的数码管。可以实现简单数学运算、逻辑运算、进制转换、连续运算等功能。-Using VHDL in quartus2 achieve calculator. Input 4* 4 matrix keyboard, the output data lines for sharing of digital control. Can achieve a simple mathematical operations, log
use-CPLD-SRAM--driving-TFT-lcd
- 用CPLD+SRAM驱动数字TFT屏的例子，希望对大家有所帮助-With CPLD+ SRAM drive digital TFT screen example, we want to help
FPGA-based-design-of-DPLL
- 采用VHDL设计的全数字锁相环电路设计，步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
32-float-point-adder
- 32位浮点加法器。我第一次上载源码你就放过我吧，我就是想看一看加法器应该怎么做。-Floating point adder
verilog
- 主要包含了用verilog语言别写的实用于视频例如LCD等显示设备的音频与视频的控制系统，其中包括了延时代码的编写模块，希望对坐显示的有所帮助!-It contains the verilog language with written and practical at the videos of other LCD and other display devices such as audio and video control systems, including the delayed p
AD9957
- ad9957的资料，内含有命令字生成器，适合使用该芯片的开发人员-ad9957 data, contains the command word generator for developers using the chip
st7565r
- ST7565R 驱动65 x 132 Matrix LCD 中文版（内含相关寄存器中文注释及初始化步骤）-ST7565R 65 x 132 Dot Matrix LCD Controller/Driver
pll
- 用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
lattice_fpga
- lattice系列fpga入门例程，非常好的理解vhdl语言及fpga开发-good data for studying the lattice s fpga
16bit-CLA
- 16 bit carry look ahead adder verilog code