资源列表
PLD_Programmable_Logic_Devices
- 可编程逻辑器件PLD Programmable Logic Devices不错的资料-Programmable logic devices PLDPLD Programmable Logic Devices good information
sin_gene
- 读取mif方式，产生正弦信号的vhdl程序-Read mif way to generate sine signal vhdl program
fulladder
- 由四位全加器通过元件例化语句设计成十六位的全加器-By four full adder component instantiated by statements designed 16 of the full adder
multi8x8
- 通过元件例化语句和信号声明实现8*8的乘法器-Cases through the components of statements and declarations to achieve the signal multiplier 8* 8
using_the_LUT_as_distributed_RAM_in_Spartan-3_FPGA
- 在 Spartan-3 系列 FPGA 中将查找表用作分布式 RAM-using_the_LUT_as_distributed_RAM_in_Spartan-3_FPGA
Using_Embedded_Multipliers_in_Spartan-3_FPGAs
- 使用Spartan-3的嵌入式乘法器，VHDL语言-Using Embedded Multipliers in Spartan-3 FPGAs
using_the_specified_MUX_in_Spartan-3_FPGAs
- 利用 Spartan-3 系列 FPGA 中的专用多路复用器-using_the_specified_MUX_in_Spartan-3_FPGAs
led_test
- LED测试程序工程文件,VHDL代码，在Quartus II 6.0中测试通过。-led vhdl test programe in Quartus II
measure
- 脉宽测量电路，低电平有效，测量的最大脉宽为256拍，若超出则报溢出-Pulse width measurement circuit, active low, the maximum pulse width measurement 256 film, if overflow beyond the reported
cnt_test
- 用Quartus ii 6.0开发的计数器工程文件，用VHDL语言编写-Counter programe used in VHDL,devlopment tool:Quartus ii 6.0
pipeline
- 用流水线构成的串行八位加法器，可以输出进位级联-With a line consisting of eight serial adder, can output binary cascade