资源列表
2364.DeSerTSW1250_v2p02
- TSW1250 code verilog code
digital-clock
- Digital clock using vhdl By. Drmody
Frequency
- 频率计，用verilog编写。语言简洁易懂。-Frequency counter, written in verilog.
adder
- 可加可减器，使用verilog编写，4位加减器。-Can be increased or decreased, verilog prepared 4 addition and subtraction.
led
- 8*8LED点阵的应用，8*8LED点阵-* 8LED lattice applications, 8* 8LED lattice
lab6
- 有关加法器的操作处理，内涵简单加法器一直到八位带进位加法器编程，附有word文档描述-Related to the handling of the operation of the adder, the connotation of a simple adder to the eight into the adder programming attached word document describes
lab7
- 有关有限状态机的设计实例，内附word文档说明-For finite state machine design examples, containing a word document instructions
lab8
- 有关fpga存储器的设计，开发板为DE2-70，内附word文档说明-Fpga memory designs, development boards for the DE2-70, containing a word document descr iptions
adder_3
- 加法器的实现，代码可直接使用，在FPGA上调试-The realization of the adder, the code can be used directly on the FPGA debugging
aes_fsl_interface
- aes to fsl with xilinx fpga
fulladder
- 全加器 东北大学秦皇岛分校 电子设计自动化 实验-Full adder Northeastern University at Qinhuangdao electronic design automation experiment
half-adder
- 半加器 东北大学秦皇岛分校 电子设计自动化 实验-Half adder Northeastern University at Qinhuangdao electronic design automation experiment