资源列表
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
verilog2
- 很不错的verilog资料 希望对你有帮助-Verilog very good information hope to help you
four_bit-data-selector
- 四位的数据选择器，可在maxplus2上运行并仿真-Four of the data selection, which can be run on the maxplus2 and Simulation
biaojueqi
- 七人表决器 当同意人数大于等于4时，投票通过。-Seven voting machines when the agreed number of greater than or equal 4, vote.
Code_for_MedianFilter33
- 数值图像处理：中值滤波设计，3*3方形窗，边缘检测的设计代码-Numerical image processing: the median filter design, the design code of 3* 3 square window, edge detection
UART
- Hardware Design with VHDL Design Example: UART
one-key-multifunction_verilog
- 采用FPGA来实现的一键多能算法，Verilog 编码，包含testbench，有详细的解释说明。-Using FPGA to implement one key multifunction algorithm, Verilog coding, including testbench, a detailed explanation.
VerilogCodingStyle
- Verilog Coding Guideline
ConterFPGA
- Implementing a Generic Conter in VHDL - FPGA
simu_NIOS
- 和NIOS功能一样的CPU，可以在FPGA上运行,Verilog源代码
baweipinlvji
- 基于vhdl的八位频率计。非常好用欢迎大家下载-Vhdl based on the eight frequency meter. Very nice welcome to download
TEXIO
- TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus