资源列表
FPGA_compile_error
- 很好的FPGA学习资料，从入门到深入，欢迎大家下载。-FPGA compile errors
扩频通信的Verilog工程
- 扩频通信的Verilog工程，对从事无线通信的工程人员有参考作用。(Spread spectrum communication Verilog project, engaged in wireless communications engineering staff reference.)
asyn_FIFOrealizedbyVHDL
- 一个比较经典的用VHDL实现的FIFO论文
vhdlfinishcpu
- 用vhdl实现简单cpu的功能,能够很好的帮助特别是初学者学习vhdl的功能!-with vhdl cpu to achieve simple function can be very helpful, especially beginners learning vhdl function!
compare
- 检测两个数是否相等，可用modelsim编程，其中包含测试程序-compare A and B,if equal ,output equal one
PLL_50MHz_to_12MHz
- Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序，50MHz分频为12MHz-Verilog HDL language，EP2C8Q208 chip， PLL frequency of simple procedures, 50MHz to 12MHz frequency
CPU2
- 利用VHDL编写的简单CPU程序，能进行简单的加减运算，有运算结果截图的
hand_shake
- 握手程序，可以完美实现跨时钟域的数据传输-handshake and testbench，verilog HDL
02_SynthesizableMATLAB
- Lab 2 – Synthesizable MATLAB This lab exercise will explore the effects that different MATLAB coding styles have on hardware. The lab has two parts, each of which begins with a short introduction. This lab exercise is based on the simple MATLAB FIR
h264
- This is an example top level module for the H264 submodules. Each implementation will differ at the top level due to differing number of video streams, resolution, and RAM type and interface. This is thus just a skeleton implementation.- T
VHDL
- 数字钟的设计，有时，分，秒，置数等功能。-Digital clock design, sometimes, minutes and seconds, buy a few functions.