资源列表
velocity_Verilog
- 速度表（velocity）要求：1．显示汽车Km/h数；2．车轮每转一圈，有一传感脉冲；每个脉冲代表1m的距离；3．采样周期设为10s； 4．要求显示到小数点后边两位；5．用数码管显示；6. 最高时速小于300Km/h。（约为83.3m/s） -use verilog to realize velocity
fft_structure
- FFT 设计的流程图，煮于使用C或者VHDL实现
DDS
- DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法
16-bit-crc16
- 16位并行输入输入的CRC16,已验证无错误-16-bit parallel data input crc16, algorithm logic has been verified
boxmuller
- 硬件生成随机数的算法，boxmiller算法-boxmiller
eetop[1].cn_Code_for_MedianFilter33
- 本程序实现3*3中值滤波的Verilog语言编写-This procedure achieved 3* 3 median filter Verilog language
exp2
- 流水灯的实验，正转反转等功能，实现流水灯顺序亮灭。-Light water experiments, are forward reverse function, water lamp light off sequentially. .
SpaceWire_IP_Rev1p06
- 日本大学开发的SpaceWire IP核，经过多年的改进，已经是第六个版本-Japanese universities developed SpaceWire IP core, after years of improvement, it is already the sixth edition
miaobiao
- VHDL语言实现秒表并在共阴数码管上动态显示十进制数值-VHDL language stopwatch and digital control on a total of negative dynamic display decimal values
Verilog.HDL
- 精通Verilog.HDL语言编程_源码，对初学者来说很好的值得借鉴-Proficient Verilog.HDL language programming _ source, good for beginners should learn
5bit-adder-subtracter
- 5 bits 的加法器與減法器合併電路之原始程式製作
NU_fp_lib_original_modules_june_2002
- fpu unt which calcultes add sub div