资源列表
CCP
- 利用CCP模块设计频率计。本程序利用CCP1模块实现一个“简易数字频率计”的功能-CCP module design using frequency meter. This procedure using the CCP1 module to achieve a " simple digital frequency meter" function
scalable_arbiter_latest.tar
- a scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speed with up to hundreds of request lines, and it grants in just a few clock cycles.
memory
- truong trinh thao tac voi memory cua VHDL
FPGA
- FPGA中的冒险现象,降低fpga的稳定性和功耗
t80_0146
- z80 ctc is good an usefull for you take it is good
serial_produce
- 设计一个能够自启动的24-1的伪随机码（111101011001000）发生器。 设计一个序列信号发生器，产生一个011100110011序列码。 实现序列1110100。测试序列码波形 个人比较欣赏第二种方法 -to design an 24-1 since the start of the pseudo-random number (111101011001000) generator. Design of a signal sequence generator to pro
EDA_tel_counter
- 在EDA教学试验箱上（忘了学校的试验箱型号了）实现电话计费器功能-EDA teaching in the chamber to achieve telephone billing function
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
water
- 基于FPGA的流水灯设计，可以检验晶振是否正常工作，时钟晶振为48M-Running water light design based on FPGA makes possible the testing of crystals is working correctly, the clock crystals of 48m
LIP1241CORE_hs_dll
- HS DLL Verilog Module
Verilog
- 对学习很好的书籍 很有助你自学 教学 适合本科生研究生博士生-Very good books on learning will help you self-doctoral teaching for undergraduate students
src
- 波形发生器，可产生方波，正弦波，三角波，锯齿波，幅度可调，频率可调-Waveform generator can produce a square wave, sine wave, triangle wave, sawtooth wave, amplitude adjustable, adjustable frequency