资源列表
uart_niosII.rar
- 基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！,Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!
2011_11_21_EEPROM_WR
- EEPROM读写控制器，源代码，仿真时序图，以及仿真结果-EEPROM read and write controller , source code, simulation timing diagram and simulation results
EPM7064-SR-Motor
- CPLD EPM7064上编的开关磁阻电机换相逻辑-CPLD EPM7064，to control SR motor
code-
- 消抖代码 应用于fpga 基础实验 常用-Debounce code commonly used in basic experimental fpga
fenpin5_5
- Verilog 语言实现利用FPGA对输入方波实现5.5分频-the frequency of a rectangular wave is divided 5.5 using the FPGA
shumaguan
- 利用VerilogHDL驱动数码管的一种方法-Use VerilogHDL drive a method of digital tube
C_Based_System_Level_Design
- SYSTEMC设计手册 C_Based_System_Level_Design-C_Based_System_Level_Design
relay_test
- Simple relay trigger
Advanced_Electronic_Design_with_VHDL
- One of these files is a design automation guideline with advanced VHDL samples. The material can be used either by beginners as well as by experienced digital designers. The second file teaches how to use PSL assertions in VHDL designs.
EDA-clockr
- EDA技术之数字时钟，带有定时闹钟功能-The EDA technology digital clock, alarm clock with timer function. . . . . . . . . . .
FPGAs_in_a_nutshell
- This rar files contains the presentation about FPGA and CPLD .
fsk_demodulation
- FSK的解调过程，及仿真图形，改变输入可以得到不同的输出结果-FSK demodulation process, and simulation graphics, change the input can have different output