资源列表
DE3_User_manual
- ALtera公司的ED3开发板，用户手册，The DE3 board has plenty of features that allow users to implement a wide range of designed circuits.-The DE3 board has plenty of features that allow users to implement a wide range of designed circuits.The Stratix® III devic
Practica_3
- SP converter in vhdl and counter and buffer
lagrange
- matlab源代码很有用那个的软件，配合许多电子软件使用-matlab source code
wannianli
- 一款基于Verilog的ＦＰＧＡ万年历开发程序-A calendar based on Verilog, FPGA development process
clock
- 本实验实现一个能显示小时，分钟，秒的数字时钟。-The experimental realization of a can display hours, minutes, seconds, the digital clock.
buzzer
- 向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调，该实验通过设计一个状态机和分频 器使蜂鸣器发出"多来咪发梭拉西多"的音调。-A certain frequency to the buzzer to send a square wave can make the appropriate tone buzzer, the experiment by designing a state machine and the divider to make the buzzer " made
serial
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。 串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值 是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通 信同步. 程
dial
- 读入拨码开关8位0 1状态在8位7段数码管相应位上显示0或1。-Reads DIP switch 8 0 1 state in the 8-bit 7-segment display the corresponding bit 0 or 1.
practical_design_verification
- Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors explain both formal tec
bch_encode
- this bch encoder verilog code-this is bch encoder verilog code
bch-code
- this a bch code wich is in visual c-this is a bch code wich is in visual c++
clock
- 该小项目实现时、分、秒计数，每个设计分一个小设计-Achieved when every second counts