资源列表
2222
- 12时钟数码管显示，芯片74161，151，248-12 clock digital display, chip 74161,151,248
VHDL_Style_Guide
- A style guide for VHDL, the popular hardware descr iptive language for the design/specification of ASICs, FPGAs and CPLDs ICs.-A style guide for VHDL, the popular hardware descr iptive language for the design/specification of ASICs, FPGAs and CPLDs I
vhdl五位加法器
- vhdl五位加法器
16bit
- 16位定时计数器内附详细说明和注释 呵呵呵呵呵呵 欢迎下载-16-bit timer counter containing detailed instructions and comments are welcome to download
sample-vhdl
- basic vhdl codes for beginers
micro_complet
- this is descr iption of microprocessor 8 bits in vhdl. enjoy
HDL_Syn_V3.1
- 哈夫曼编码 包括synthesis优化。 Huffman encoding verilog code including synthesis optimization.-Huffman coding involves synthesis optimization. Huffman encoding verilog code including synthesis optimization.
tdmddc_v61
- Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
DCT_1D
- 一维DCT变换的verilog源码，可用于JPEG算法优化的参考。程序中用到的算法称为“扭卷积”，可参考相关IEEE paper
8051core-Verilog
- MCU 8051源码经过FPGA验证，功能全-mcu 8051 code
eclock
- 数字钟 分模块设计 实现基础功能 VHDL编写 -eclock vhdl
VHDL_Style_Guide
- Great guide for writing VHDL