资源列表
myCLK
- 24Mhz的频率分成2Mhz的频率。 再由一个I/O口输出。-The frequency of 24Mhz into2Mhz frequency，Again by an I/O port output.
exp1
- 带控制端口的加法器，用于完成两个向量的相加。-To the control port of the adder, to complete the two bit vector addition.
exp2
- 无控制端口的加法器，用于完成两个位向量的相加。-No control port of the adder, to complete the two bit vector addition.
VerilogHDL
- 《设计与验证：VerilogHDL》的配套源代码，有丰富的例子，有利于初学者使用-Design and Verification: Verilog HDL "supporting source code, a wealth of examples, for beginners
exp3
- 带控制端口的乘法器，用于完成两个向量的相乘。-With the control port multiplier, for the completion of the two vector multiplication
exp4
- 比较器，用于比较两个位串所代表的整数的大小。-The comparator is used to compare two, represented by the bit strings of integers
demo7-uart
- FPGA EP2C5的串口代码，FPGA新手学习的很基础的代码-about the FPGA IC:EP2C5 uart code.it is use for the fresh one.
qiangdaqi
- 电子抢答器 可以容纳四组参赛队进行比赛具有强大信号和锁存能力 自动计分 犯规减分- answerphone
matlab1
- disaininig harmonic FPGA ic sourcecodes/documents
relogio_estrutural
- vector decodificador 8 a 2 enjoy-vector decodificador 8 a 2 enjoy...
Square_VGA
- It draws a square in a VGA screen. It works with Xilinx with the spartan 3E starterkit
VGA_sync
- It is a game for spartan 3E starterkit in a VGA screen