资源列表
my_uart
- 数据收发器，串口模块，可使用串口调试小助手来进行数据收发，验证模块的功能-Data transceiver, serial module, you can use the serial port to debug his assistant to send and receive data, verify the functionality of the module
nios2_ucos2
- 基于Altera的FPGA配置的Nios2软核，移植了uC/OS2操作系统。实现的功能包括1602字符液晶驱动，基于中断的4*4矩阵键盘检测，流水灯。所有C文件位于\software\nios2_hello_ucosii目录下。 -Embedded Nios2 System based on Altera s FPGA, with uC/OS2 RTOS transplanted. Function included: 1602 character LCD display, 4*4 matr
miaobiao
- 秒表计时功能,可以从零记到九十九，可以暂停，可以清零。-Stopwatch functions, from zero in mind to 99, you can pause, can be cleared.
rotary
- 采用verilog语言编写的rotary encoder程序，可以识别出旋转方向。-Rotary encoder verilog language program, you can identify the direction of rotation.
Cipher-lock.doc
- VHDL实现四位电子密码锁，并在12864液晶显示屏上显示-VHDL implementation of the four electronic locks, and 12864 on the LCD screen
left_right_leds
- 旋转编码器的vhdl驱动程序，巧妙的消除按键噪声。-The rotary encoder VHDL driver, clever elimination of key noise.
1
- 基于VHDL的1602驱动程序，采用状态机的方法编写-Based on VHDL-1602 driver, prepared by the state machine
DACtest
- Spartan 3E - DAC- VHDL. It is a vhdl code for Xilinx Spartan 3E fpga to run ADC and AMP on the board via SPI interface.
VHDLbasic_cal
- VHDL的加、减、乘、比较等基本运算的源代码-VHDL add, subtract, multiply, compare the source code of the basic operations
135-examples--for-verilog
- 135 examples for verilog
frequency
- 等精度频率计（FPGA部分），通过单片机发送频率控制字给FPGA，FPGA实现计数，再将计数结果发送给单片机后进行数据处理最后发送到数码管或液晶屏显示待测频率-Precision frequency meter (FPGA part) by the single-chip transmit frequency control word to the FPGA, FPGA, to achieve the count, and then finally sent to the digital dat
DDC_VHDL
- DDS信号发生器，可以生成方波，三角波以及正正弦波等，只要稍微修改下输入数据即可生成任意的波形。-DDS signal generator can generate a square wave, and some small modifications to the next input data to generate arbitrary waveforms.