资源列表
CNT_24
- 用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
AlteraFPGA
- 在Altera的FPGA开发板上运行第一个FPGA程序，以后我还会陆续发布这方面的代码
PWM Motor feedback
- Verilog code for learning for purpose
sram2lcd
- sram、lcd驱动；将彩条数据写入SRAM，然后反复读出数据显式在tft_lcd上-sram, lcd driver the color of the data is written to SRAM, and then read data explicitly repeated on the tft_lcd
verilogshiyansoure37
- verilog实验的基本程序，包括状态机、数码管、流水灯、蜂鸣器、点阵、键盘等等，超详细的程序、适合初学者-verilog basic experimental procedures, including the state machine, digital control, water lights, buzzers, dot matrix, keyboard, etc., super detailed procedures, suitable for beginners
shuzishizhong
- 此代码是FPGA的数字时钟代码，使用的是verilog语言。-This code is the FPGA' s digital clock code, the use of the verilog language.
taxi-vhdl
- 出租车计费器 硬件描述语言 出租车计费器 MAX+PLUS软件 数字系统
LIP1759CORE_audio_dsp32_decoder
- Audio DSP32 Decoder Verilog Module
digital-clock-in-vhdl
- digital clock display
fft_8
- 基二8点fftverilog实现。经过modelsim仿真通过-Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation
mma7455-IIC-chengxu-C52
- mma7455IIC测试程序C52 外加1602显示和串口数据发送-mma7455IIC test program to display and C52 plus 1602 serial data transmission
f340_pov_led_
- 利用十三个发光二极管显示旋转，显示时钟，还有汉字-Using thirteen LEDs display rotation, display clock, there are Chinese characters