资源列表
FPGA_nCLK.rar
- VHDL语言的高频时钟分频模块。一种新的分频器实现方法。,VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
clk_div
- Thia is VHDL code for clock divider
VHDL-node
- VHDL的一些实验代码，其中有4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现-Some experiments of VHDL code, which has four reversible counters, four reversible binary code- Gray code converter design, sequence detection Design, ROM-based sine wav
beep
- fpga cpld verilog hdl 语言 代码程序 beep 控制
cnt24_t
- 这是二十四进制计数器的源程序，有需要的同学可以参照一下！-This is 24 hexadecimal counter source, needy students can refer to you!
rc4
- RC4 is the most popular stream cipher in the domain of cryptology. RC4 consist of two algorithms Key Scheduling Algorithm (KSA) and Pseudo-random generation algorithm (PRGA).
4-16
- 4-16译码器。按0000-1111编码，相应的得到输出。下载后可实现-4-16 decoder. Encoded by 0000-1111, the corresponding receive output. Download can be realized
lab3_VHDL
- 这是基于VHDL的编程练习，适合于初学者学习VHDL编程，通俗易懂，简明扼要。
cpu01
- 一个简单的cpu的VHDL源码描述，希望对大家有点用呀-Cpu a simple descr iption of the VHDL source code, I hope all of you a bit with it
ethernet
- 以太网验证平台 以太网验证平台-Ethernet Verification Platform
0514
- 16位4*4寄存器组 可以用于模拟主机系统设计时使用-16B reg
8by8multiplier
- Verilog HDL for 8*8 multiplier-Verilog HDL for 8*8 multiplier..