资源列表
sy3
- 用两片74194扩展成8位双向移位寄存器-Extended to 8-bit bi-directional shift register with two 74194
cpld_altera
- DM642核心板采用CPLD扩展地址 CPLD部分程序 可直接烧写-DM642 core board using CPLD CPLD extended address part of the program can be directly programmed
verilog-i2c-master
- i2cccccc masyettttttttttttt
Verilog_m_lx
- 一个简单的verilog小程序，适合初学者学习(A simple Verilog small program, suitable for beginners to learn)
FFTs_in_FPGAs_and_ASICs
- - FFTs_in_FPGAs_and_ASICs
xapp495
- 居然没有找到verilog 这是xilinx的一个hdmi的标准核 我测试使用通过-Actually did not find verilog xilinx an hdmi standard nuclear my test use by
PIANo
- （1）下载“KX232_PIANO_C5T”文件夹中的sof文件。 (2) 接上串行通信线，与PC机通信。 （3）在“FOR_PC_FILE”文件夹中，双击打开上位机软件“SEND”,按键盘上的“1、2、3.。。”即可弹琴。SEND窗口即显示对应的ASIC码。-(1) Download " KX232_PIANO_C5T" folder in the sof file. (2) connected to the serial communication lines, a
BEEP-OF-FPGA
- fpga的程序，大家可以看一下，上传分享，希望有帮助。-fpga program, we can look at, upload and share, want to help.
SPI_FireWall
- verilog spi file with testbench
COM_REV
- 基于FPGA的串口接收程序,标准通用的串口接收程序-FPGA-based receiver program
SEVSEG
- 简单的数码显示例子,初学非常好。。希望能帮助大家-simple digital display
FPGA-clock
- 介 绍了为PET（正电子发射断层扫描仪）的前端电子学模块提供时间基准而设计的一种新型高频时钟扇出电路。-Introduced for PET (positron emission tomography) of the front-end electronics module is designed to provide time for a new benchmark high-frequency clock fan-out circuit.