资源列表
Clock-experiment
- 数字时钟程序，亲自在实验室做过这个实验，实验成功。-Digital clock program, personally done this experiment in the laboratory, the experiment was a success.
ROBOT_CONTROL
- code for xilinx spartan fpga to make robot path control by detecting obstruction using ultrasonic sensor
fwcode
- high-level data link control procedure VERILOG CODE
HDB3
- HDB3协议的编解码，并有对于频率为32768HZ的仿真图，并且将时钟线数据线合一，并有同步时钟提取的模块。-failed to translate
PWM_IP_TEST
- 自定义PWM的IP核 符合avalon总线格式-Custom PWM IP core is in line with the avalon bus format
RS_FPGA
- RS编码器译码器的FPGA实现原理，优化，在光通讯中应用-failed to translate
uartfifo
- 基于FIFO的串口发送机设计。主要实现一个串口发送器功能，该发送器的数据是从FIFO 中读取的。也就是说，只要FIFO 中有数据，串口发送器就会启动，将数据发送出-FIFO-based serial transmitter design. A serial transmitter function of the transmitter data is read from the FIFO. In other words, as long as there is data in the FIFO,
ise
- 设计微处理器基本输入输出系统，通过拨码开关控制LED灯的亮灭（开关为高电平时灯亮,反之则灯灭），并从键盘输入的字符可以在超级终端回显-Design microprocessor basic input output system, is controlled by DIP switch LED turns on or off (switch is high, the lights, the lamp is off and vice versa), and characters can be en
ise
- 设计微处理器基本输入输出系统，实现投票系统，通过拨码开关（SW0~SW3）输入，当BTN North (V4)键被按下时收集投票。若投票数大于或等于3票，则点亮板上的LD0，并在超级终端输出“Pass!”。若投票数小于3票，则不点亮LD0，并在超级终端输出“Lose!”-Design microprocessor basic input output system, voting system, input via DIP switch (SW0 to SW3) to collect the b
ise
- 实现两个2位二进制数的相加，两个数A和B分别对应于板子上的（SW3,SW2）和(SW1,SW0)，其中SW3，SW1为高位。BTN 设计微处理器基本输入输出系统，North (V4) 按键为运算执行键。当BTN North按下时，两数相加的结果将通过LD3~LD0显示，其中LD3为最高位，LD0为最低位。同时，超级终端上也会输出计算结果。-Design microprocessor basic input output system, the sum of two 2-bit binary nu
ise
- 设计微处理器命令处理系统，实现的功能：通过系统的串口输入指令TIME控制时钟显示时间。-Design microprocessor command processing system, functions: control the clock display time through the system s serial input command TIME.
ise
- 设计微处理器命令处理系统，通过系统的串口输入指令显示闹铃状态。-Design a microprocessor command processing system through the system s serial input command to display the alarm status.