资源列表
fashengqi
- 通过读取rom的方式，调频调幅选择波形的信号发生器。已经调试过 verilong-based on rom to create a kind of generator which can change frequency, amptilude and waveform.
42VHDL-code
- 42个 VHDL实例 是学习VHDL的必备宝典 强烈推荐-42 VHDL example is the essential book for learning VHDL is strongly recommended
R232_total
- 用VHDL语言在FPGA上实现RS232的通信-RS232 communication is implemented on FPGA using VHDL language
E01
- basys2开发板组合逻辑电路演示，输入为SW-0和SW-1,输出为LED0-LED5-basys2 development board combinational logic demo，there are two input,SW0 and SW1. output is LED0-LED5
memory_cores
- 包括标准的FIFO的设计以及一种通用的CACHE设计。-failed to translate
Verilog-HDL-Synthesis-=
- Verilog HDL Synthesis A Practical Primer-failed to translate
traffic
- 基于FPGA的交通灯控制系统，使用verilog语言书写，quartus II运行-FPGA—veriliog,Light controlor system
naozhong
- 万年历并且带闹钟功能，时间可调,闹钟可调，还有响铃-failed to translate
cal
- verilog设计计算器顶层模块，无下层模块需自行添加-verilog based calculator
spiV
- FPGA spi通信协议，很全，大家参考，希望对大家有用。-Fpga spi Communication protocol, very full, we refer to the hope that useful.
coregen_overview
- core generator vhdl book
coregen_tutorial
- core generator vhdl book