资源列表
ad9889b_ctrl
- AD9889B配置程序 支持CSC 支持EDID解析 支持热插拔-AD9889B configuration program supports hot-swappable CSC supports EDID resolution
FPGA---Electronic-clock
- FPGA中用VHDL编写24小时普通电子时钟，可实现复位，程序整体写成，没有用到例化语句。-Electronic clock
88091
- 马威尔网卡驱动 交换机驱动 实现8路100M网*换 实现包自动转发 -Marvell LAN Driver 8-way switch drive to achieve 100M Ethernet port switching implementation packages automatically forwarded
iic_88091
- 实现88091驱动 带iic驱动 可以通过网管控制盘 通过IIC更新配置参数-Achieve 88,091 iic driver can drive belt through the network control panel update configuration parameters through the IIC
touch-screen
- 基于DE0的触摸屏设计 VHDL 语言 大作业-DE0-based touch-screen design VHDL language major operations
eat-bean-game
- 小时候的吃豆子游戏 有两个幽灵追赶 VGA显示-Childhood Pacman game has two ghosts catch VGA display
lcd_test
- LCD显示 可以从A到Z 循环显示 基于xilinx板子-LCD display can cycle from A to Z on xilinx board
8255
- 可编程并行接口芯片8255A VeriLog实现-8255A programmable parallel interface chip
FPGA-application
- 28个FPGA应用开发代码实例，可供初学者学习使用-28 FPGA application development code examples
alarm
- 利用vhdl和verilog两种方式可以实现的fpga芯片的数字钟，其中包含多个可设计改动的个性化模块。源代码利用quartusii平台写作，可移植性很强。-Using vhdl and verilog fpga can be achieved in two ways-chip digital clock, which includes several design changes personality module. Source code using the platform quartu
calculator
- 利用verilog和vhdl两种语言写作的计数器，还有个性化设计模块，利用quartusii平台写作。-Use verilog and vhdl counter writing in two languages, as well as personalized design module, using the platform quartusii writing.
booth
- 比较好的带符号数乘法的方法是布斯(Booth)算法。它采用相加和相减的操作计算补码数据的乘积。Booth算法对乘数从低位开始判断，根据两个数据位的情况决定进行加法、减法还是仅仅移位操作。-Signed multiplication better approach is to Booth (Booth) algorithms. It uses the operation of addition and subtraction calculations complement data of the