资源列表
alert
- eda电子钟闹钟模块的实现 -digital clock alert digital clock alert digital clock alert digital clock alert
conunt
- eda电子钟计时模块的实现 eda电子钟计时模块的实现 eda电子钟计时模块的实现-eda count eda count eda count eda count eda count eda count eda count eda count
CNT4
- ise组合逻辑电路中的4选1多路选择器+仿真文件-ise combinational logic circuit 4 to 1 multiplexer+ simulation file
count_8
- ise13.2环境下编写的8位二进制计数器+仿真波形-ise13.2 environment prepared by the 8-bit binary counter+ simulation waveforms
DFF1
- ise13.2环境下编写的D触发器+仿真波形-ise13.2 environment prepared by the D flip-flop+ simulation waveforms
f_adder
- ise13.2环境下vhdl编写的全加器+仿真波形-ise13.2 vhdl prepared under the full adder+ simulation waveforms
h_adder
- ise13.2环境下VHDL编写的半加器器+仿真波形-ise13.2 environment half adder in VHDL simulation waveform control+
mux21
- ise13.2环境下VHDL编写的2选1多路选择器+仿真波形-ise13.2 environment, VHDL, 2-to-1 multiplexer+ simulation waveforms
SCHK
- ise13.2环境下VHDL编写的8位序列检测器+仿真波形-ise13.2 environment in VHDL 8 sequence detector+ simulation waveforms
bw_scoresource
- This the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.-This is the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.
laboratory1_1
- DE2指导实验之实验1第一部分 具体实验指导书（英文版）-Instructed Excises 1.1 of DE2
M12
- VHDL硬件描述语言实现M12序列，可以用作白噪声，码率可调-VHDL hardware descr iption language M12 sequence can be used as white noise, adjustable rate