资源列表
Ram_FIFO
- VHDL硬件语言实现FIFO，管道,经过测试，很好用-VHDL hardware language FIFO, pipe
cordic
- VHDL实现cordic算法，精确度非常高，模块化设计，带显示功能-VHDL implementation cordic algorithm, a very high accuracy, modular design, with display function
ep1c12_32_vga
- 完整的VGA时序及其彩条显示，棋盘格显示，注释完整-Complete VGA timing and color bar display, checkerboard display, annotate complete
multiclock
- 以VHDL为基础的多功能数字钟的实现功能程序，包括时钟，闹钟，计数等功能。-In VHDL-based implementation of multi-function digital clock procedures, including clock, alarm clock, counting and other functions.
god
- This paper presents a novel robust number theoretic transform called inverse Gray Robust Symmetrical Number System (IGRSNS) and proposes its application for CDMA systems. The transceiver structure for three moduli IGRSNS-CDMA with one redunda
IC035os142_max_worsecase
- 数字电路设计，基本单元逻辑综合库，Worsst case 高温慢速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case conditions of high temperature slow libraries, available dc_shell environment called for RTL synthesis.
IC035os142_min_bestcase
- 数字电路设计，基本单元逻辑综合库，Worsst case 低温高速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case conditions of high temperature slow libraries, available dc_shell environment called for RTL synthesis.
IC035os142_typ
- 数字电路设计，基本单元逻辑综合库，Worsst case 室温典型速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case temperature conditions typical speed database available dc_shell environment called for RTL synthesis.
IC035os142_min_minuse
- 数字电路设计，基本单元逻辑综合库，Worsst case 负温度，极端条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case negative temperature, extreme conditions, libraries, available dc_shell environment called for RTL synthesis
sopc_seg_2c20
- 基于SOPC实现数码管的动态扫描显示 四位一体数码管-Based on SOPC implementation of digital control of dynamic scanning display
Watch
- 秒表功能电路,实现起动、停止等秒表计时功能。-Stopwatch function circuit, start, stop, etc. stopwatch function.
I2C-code
- I2C总线协议 Verilog源代码.试过，没有错误！可以直接使用-I2C bus protocol Verilog source code. Tried, no errors! Can be used directly