资源列表
shumaguan
- verilog 写的，基于CPLD 的数码管实验，输入端是430单片机，cpld做了38译码器和8位所存-verilog written CPLD-based digital tube experiments, the input is 430 single, cpld made 38 decoder and 8 kept
VHDL_ReversibleCounter
- 可逆计数器(两位十六进制,以十进制方式显示即从00,01数到14,15然后00,01再到根据10hz晶振(低频都可选,视板子情况而定)作为时间脉冲计数,rst键可以重置(清零 )计数器,drct键选择加法计数还是减法计数.-2-bit-Hexadecimal Reversible Counter(decimal display)
Alarm_Microblaze_ASM
- A Alarm system writed in Assembly to use on a Microblaze VHDL project.
dds_again
- 基于FPGA的DDS。可以产生三种波形：正弦，方波，三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。-FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.
MyFrequencyDesign
- 基于单片机msp430和cpld的高精度频率计。测频范围为0至20MHz。误差在万分之一。可以测量0至100KHz周期，脉宽。-Msp430 microcontroller-based and cpld precision frequency meter. Frequency measurement range of 0 to 20MHz. Error in a million. Can measure 0 to 100KHz cycle, pulse width.
rng
- wishbone规格下的rng代码的实现，自己编写顶层模块可以在modelsim下实现仿真-wishbone rng specifications under the implementation of the code, you can write your own top-level module under modelsim for simulation
ltc1068
- ltc1068简易数控滤波器（1k-20kHz）verilog-ltc1068 Simple NC filter (1k-20kHz) verilog
Xilinx-stacked-silicon-interconnect-technology.zi
- Xilinx stacked silicon interconnect technology Xilinx stacked silicon interconnect technology
SmartFusion2-Data-sheet-
- SmartFusion2 Data sheet SmartFusion2 Data sheet -SmartFusion2 Data sheet SmartFusion2 Data sheet SmartFusion2 Data sheet
3333333
- 基于vhdl语言的同步fifo的宏模块调用程序，可学习fpga的宏模块调用方法-Synchronous fifo vhdl language-based macro block the calling program, can learn fpga macro module calls methods
FPGA
- 分频器是FPGA设计中使用频率非常高的基本设计之一,该文详细介绍了任意数分频的设计方法-Divider FPGA design is a very high frequency of use is one of the basic design, the paper details the design of any number of methods divide
FPGAstudy
- verilog books .it is worth reading