资源列表
encoder_83
- 这是基于Quartus 2开发环境和verilog hdl语音编译的83解码器-This is based on Quartus 2 development environment and compiler verilog hdl voice decoder 83
voter_VHDL
- 这是基于Quartus2开发环境和vhdl语音编译的表决器-voter basic on vhdl and Quartus2
matlab-and-verilog-fir4_3
- 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
verilog-generate
- 很实用的verilog中generate语句使用方法整理 -Useful in verilog generate statements use method
Xilinx-design-timing-constraints
- 很有用的Xilinx时序约束设计资料，很适合初学者-Very useful Xilinx timing constraints, design data, is very suitable for beginners
LCD1602
- 通过编写verilog语言完成数据的在液晶LCD1602显示-By writing verilog language to complete the data displayed on the LCD LCD1602
KEYS
- 在ISE环境下按键子程序完成多个独立按键的控制-The ISE environment keys subroutines multiple independent control keys
ADC0809
- ADC0809的verilog实现 及仿真的文件 和仿真的波形图-ADC0809 implementation and simulation of verilog files and simulation waveforms
LED8x8
- 8x8点阵的verilog实现，包含仿真testbench，和仿真的波形图-8x8 dot matrix verilog achieve, including simulation testbench, and simulation waveforms
booth-16_16-multiplier
- 由verilog编写的利用booth编码的16*16有符号乘法器的代码，没有pipeline-a 16*16 multiplier with booth coding by verilog
prng
- 采用线性同余法的素数模乘同余发生器产生随机数,采用5级流水线设计-Using a linear congruential method prime modulus multiplicative congruential random number generator, using five pipeline design
adc_ads7842
- 由system verilog编写的adc_ads7842的驱动模拟程序-Adc_ads7842 verilog prepared by the driving simulator