资源列表
attachments
- fpga master fofo design continous data transmission
library ieee
- 四种模式：一共六个灯，1从左到右闪2从右向左闪3从中间向两边4从两边向中间(Four modes: a total of six lights 1 from the left to the right 2 from right to left, 3 from the middle to the two sides to the middle 4from both sides to the middle)
wb_counter-1.0.1.tar
- wishbone counter for fpga
I2CHDL
- IIc时序逻辑的VHDL源代码，便于时序的调试(VHDL source code of IIc time series logic, easy to debug time series)
fir4tap using array
- 4 tap fir filter using by passing multiplier
Basys-3-Keyboard-2016.4-1
- Demo for keyboard, basys3 made by digilent
2_FFs
- Flipflop with all possible combination verilog
pinlvji
- 本文件用于测波形频率的verilog代码，是典型的数字频率计的源代码(This document is used to measure the frequency of the Verilog code, the source code of a typical digital frequency meter)
uart程序
- UART接口程序，UART字符发送函数，UART字符接收函数，主函数等(the connect of uart)
FP_adder
- 32 bit floating point adder with testbench
FP_divider
- floating point divider for 32 bit with test bench
FP_multiplier
- Multiplier for 32 bit with test bench using verilog HDL