资源列表
ADDA_control_VHDL
- VHDL语言的ADDA（模数数模置换）控制，用于程控交换机功能，与DSP和ADDA芯片配合-VHDL language ADDA (analog-to-digital digital-analog replacement) control, for program-controlled switchboard function, with the DSP and ADDA chip with
nios-uart
- 基于nios ii uart 驱动 带接收和发送缓冲区 很少的改动可以任意添加多个串口-Based on nios ii uart driving belt can transmit and receive buffer rarely changes can be more than add a serial port
45654
- FPGA方面的学习资料，老师整理，非常有用，希望能够对大家有所帮助，做设计时用到-FPGA aspects of learning materials, teachers organize, very useful and we hope to be able to help, so the design used
SRAM_16Bit_512K
- 一个sram的源码程序，它是256kbx16bit的sram
relay
- code for relay in mobile jamming
demo_2012_2
- KD_CPU,8位实现基本功能的cpu，基于verilog-KD_CPU,8bit CPU with basic functions, base on verilog
spi-uart
- 这个程序是C8051F30x设备通过 spi 通讯然后从串口发送的例程 具有 spi 跟串口的初始化操作-This program sets up the GPIO pins on the C8051F30x device for the correct functionality, then uses the SPI_Transfer function to send and receiveinformation through the SPI pins. As information
yui_dy42
- Linear array using cut than learning laid upon the right control of the main sidelobe ratio, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. Using high-order cumulants of MPSK signal modulation recognition.
scr
- 4阶24倍抽取CIC滤波器设计-4th order 24 times CIC decimation filter design
waveform_vhdl.zip
- 多功能波形发生器VHDL程序与仿真,正弦、三角、锯齿、方波vhdl 实现,Waveform vhdl Generator
independent
- security gate controller
clock
- verilog的数字钟代码，在XILINX上运行，可以手动设置时钟、闹钟，可报警-digital clock verilog code running on XILINX, you can manually set the clock, Alarm Clock, alarm