资源列表
traffic-light-CPLD
- 利用cpld实现交通灯的控制时序，实现软件microwin使用梯形图编译成功，并在西门子S7-200PLD成功运行。 -Cpld control the timing of traffic lights, the software microwin compiler, and run successfully in Siemens mc200PLD,
jkcfq
- JK触发器，适合初学者用，上实验课使用杠杠的-JK flip-flop, suitable for beginners, using a lever on the experimental class! ! !
dds
- 用VHDL语言实现的dds信号的源代码，已测验，可通过-dds in vhdl
DI
- 这是一个计算占空比的VerilogHDL程序，输入一个待测信号，然后输出Ton,Toff.单位是us-This is a the duty cycle VerilogHDL calculated program to input a signal to be measured, and then outputs Ton, Toff. Unit is us
pskdem_fixed
- psk解调的定点仿真模型。另外DEC2HEX.C负责将十进制的数据文件转换为十六进制的数据文件，因为MATLAB输出数据格式为十进制，而NC-VERILOG能够读取的数据格式为十六进制，所以需要转换。-psk demodulation of the fixed-point simulation models. In addition DEC2HEX.C responsible for the data file is converted to decimal hex data file, as
i2c_verilog
- I2C Master IP 核 I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between
FPGAPLJ
- FPGA频率计程序，实现高频率的频率计数，采用LCD1602进行显示，对需要采用频率精度较高的有较大帮助。-FPGA frequency meter program, to achieve high a frequency count using LCD1602 display, to require the use of high frequency accuracy greatly help.
8.23-
- -功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 -- Function: 4 kinds of common sine, triangle, sawtooth, square wave (A, B) the frequency, amplitude controllable output (square wave- A duty cycle
OCIDEC_Drivers
- OCIDEC ATA driver source code
snake_spartan3e
- Snake Game on Spartan 3e
RTL-files
- ahb2apb bridge top module.
IIC_verilog
- IIC控制器，源代码verilog,WISHBONE总线-IIC controllers, the source code verilog