资源列表
reading_dna
- dna driver verilog code
test
- the carry save adder program in verilog
lcd.ucf
- the lcd ucf file in xilinx ise
viterbi213
- （2,1,3）维特比译码器，具有一定纠错性能-Viterbi decoder
mulbinarytree
- 16位二叉树乘法器（阵列乘法器），VHDL实现-16-bit binary tree multiplier (array multiplier), VHDL realization
FPGA_project
- 基于FPGA目标版上采集码盘数据，并将其发送至上位机-Based on the FPGA target version of the collecting the code disk data and send it first bit machine
f_changed_SPWM
- 用RAM存储波形，简单的实现了频率可调的spwm波，可以根据需要更改RAM的内容，即更改输出波形。-RAM memory waveform frequency adjustable spwm wave, may need to change the contents of the RAM, change the output waveform.
f_p_changed_wave
- 频率相位均可调的数字信号发生器。开发环境：QuartusII8.0-Digital signal generator frequency and phase can be adjusted. Development Environment: QuartusII8.0
frequency_measure
- 简单实现数字频率计，开发环境：Quartus8.0-Simple digital frequency meter development environment: Quartus8.0
dutyfactor
- 可调占空比程序，开发环境：Quartus8.0-Adjustable duty cycle of program development environment: Quartus8.0
f_changed_sin_wave
- 用RAM实现频率可调正弦波发生器，开发环境：Quartus8.0-To frequency tunable sine wave generator development environment: Quartus8.0 using RAM
f_changed_square_wave
- 用RAM实现频率可调的方波发生器，开发环境:Quartus8.0,个人实验成功，放心使用。-RAM adjustable frequency square wave generator development environment: Quartus8.0, personal experiment is successful, rest assured.