资源列表
wannianli
- 数字万年历，可显示年月日，时分，具有闰年功能。VHDL语言编写，利用DE2平台实现。-Digital calendar, date, time, with a leap year. VHDL language using DE2 platform.
Registers
- Registers behavioral,simulation and gate implementation code
RAM-Module
- Random Access Memory Module
fsmd_examples
- fsm有限状态机加datapath的一个例子-fsm finite state machine plus datapath example
paomiao
- 用Verilog编写的跑秒程序，最大时间30秒，适合于各种场合的倒计时。-Written using Verilog stopwatch program, the maximum time of 30 seconds, the countdown is suitable for a variety of occasions.
vmm_golden_reference_guide_jan_2010
- advanced vhdl guide (ovm)
DIGITAL_TIMER
- 用FPGA开发的多功能电子时钟，能够设置闹钟，调试-FPGA development of multi-functional electronic clock, set the alarm, commissioning
timer
- this 1 ms timer and 1024 counter .-this is 1 ms timer and 1024 counter .
I2C
- 自己学习时写的，实现了以单片机作为主机的I2C单用户系统。只限于功能仿真，完成协议的要求。-This project is determined to realize the I2C protocol in which a MCU is the master.
EP1_MUX41
- 是一个基于Quartus的程序，主要功能是四选一，还包含有蜂鸣器。用VHDL语言编写，可以在EP2C5T144C8的板子上实验。-A based Quartus procedure, the main function is four, but also contains a buzzer. Using VHDL language, experimental on in EP2C5T144C8 board.
PS2shumaguan
- 是一个用按键控制数码管的实验程序，编写语言为VHDL，该程序可用，已经实验过，使用EP2C5T144C8的开发板。-A button control digital tube experimental procedures, writing language VHDL, the program is available, has experimented, using EP2C5T144C8 development board.
fifo
- 这是一个基于FPGA的fifo程序，使用环境为Quartusruan软件，已经过实验，成功。-This is an FPGA-based fifo program, the use of the environment as Quartusruan software has been experimental, successful.