资源列表
1.Area-Efficient-Carry-Select-Adder
- Area efficient carry save adder
ade
- Verilog code for modified serial multiplier
Adder
- 8bit low power pipelined adder-8bit low power pipelined adder
SDRAM_Source
- DE2 Board SDRAM Controller
SDRAM
- DE2 SDRAM Controller Pin Configuration Set-DE2 SDRAM Controller Pin Configuration Set!!!
RS232
- DE2 Board RS232(UART CHIP Level)
FLASH
- DE2 Board FLASH Memory Controller
viterbi-deoder
- viterbi decoder with constraint length 7,4
booth.vhd
- this the source code for booth s multiplier. used to low power dsp architecture.-this is the source code for booth s multiplier. used to low power dsp architecture.
code
- 可编程器件课程实验相关代码。硬件描述语言中不同的描述，会综合出不同的硬件电路。-The programmable device curriculum experiments relevant code. The descr iption of the hardware descr iption language, will be integrated hardware circuit.
pnsequence.v
- pn sequence generator in verilog
FPGA
- 基于FPGA的视觉电生理图像刺激系统的设计-Based on the design of FPGA visual electrophysiology image stimulation system