资源列表
124076017.tar
- code for data comperssion
rs422
- RS-422的VHDL实现，代码测试能用-RS-422 VHDL implementation code test can be used
M058_M0516-Product-Brief-SC-V1.0
- 新塘M058_M0516 Product Brief SC V1.0-M058_M0516 Product Brief SC V1.0
booths
- booths multiplier vhdl program
lab5
- Verilog 程序 可以实现带进位的8bit加法和减法-The Verilog procedures can achieve 8bit addition and subtraction with carry
fp_prj
- 这是自己编写的一个流水灯程序 通过修改cs的值可实现方向的翻转 但是没有接入案件功能 需要的同学可自行添加 使用quartus12编译 modelsim10.1仿真-This is a program I have written a light water can be achieved by modifying the value of cs direction flip but no access cases feature requires students own add use qu
verilog
- 用verilog编写的实用电话计费器程序 -The telephone billing procedures written in verilog
S16_ADC_NEW
- ADC7923的verilog程序，spi配置的，测试可用-ADC7923 verilog program, spi configuration, testing available
fir
- 16阶的FIR滤波器的verilog文件，包含了测试报告。-16 order FIR filter verilog file contains a test report.
DDSFPGA
- 在fpga中实现的DDS程序，程序，测试可用-DDS program, implemented in fpga program, the test can be used
video_add_program
- 用FPGA实现的视频叠加系统，电子设计大赛的，程序-FPGA implementation of video overlay system, Electronic Design Contest, the program
stack_16x8
- VHDL语言写的16x8堆栈模块设计，存储器全满时给出信号并拒绝继续存入；读出时按后进先出原则；存储数据一旦读出就从存储器中消失；有相应的testbech文件，经测试可用。对小型设计很有用！欢迎下载交流学习。-Write VHDL 16x8 stack module design, memory signal is given full and refused to continue the deposit readout LIFO principle store data read out